Intel E7-4870 v2 CM8063601272606 Manuel D’Utilisation
Codes de produits
CM8063601272606
Integrated I/O (IIO) Configuration Registers
464
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
11:7
ROS_V
0x0
SwRID[4:0]:
Switch Routing ID.
This field is concatenated with SwRID[6:5] to form SwRID[6:0]. See
This field is concatenated with SwRID[6:5] to form SwRID[6:0]. See
description for SwRID[6:5].
6:5
ROS_V
0x0
Fmt[1:0]:
Format.
This field combined with the Type field specifies the transaction type.
This field combined with the Type field specifies the transaction type.
The encodings for valid {Fmt[1:0], Type[4:0]} combinations:
{2'b00, 5'b0_0000}: Memory Read
{2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
{2'b00, 5'b0_0001}: Memory Read Locked
{2'b01, 5'b0_0001}: Memory Read with extended address Locked
{2'b10, 5'b0_0000}: Memory Write
{2'b11, 5'b0_0000}: Memory Write with extended address
{2'b00, 5'b0_0010}: I/O Read
{2'b10, 5'b0_0010}: I/O Write
{2'b00, 5'b0_0100}: Configuration Read Type 0
{2'b10, 5'b0_0100}: Configuration Write Type 0
{2'b00, 5'b0_0101}: Configuration Read Type 1
{2'b10, 5'b0_0101}: Configuration Write Type 1
{2'b00, 5'b1_1011}: Trusted Configuration Read
{2'b10, 5'b1_1011}: Trusted Configuration Write
{2'b00, 5'b0_1010}: Completion without Data
{2'b10, 5'b0_1010}: Completion with Data
{2'b00, 5'b0_1011}: Completion without Data Locked
{2'b10, 5'b0_1011}: Completion with Data Locked
{2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe*
{2'b00, 5'b0_0000}: Memory Read
{2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
{2'b00, 5'b0_0001}: Memory Read Locked
{2'b01, 5'b0_0001}: Memory Read with extended address Locked
{2'b10, 5'b0_0000}: Memory Write
{2'b11, 5'b0_0000}: Memory Write with extended address
{2'b00, 5'b0_0010}: I/O Read
{2'b10, 5'b0_0010}: I/O Write
{2'b00, 5'b0_0100}: Configuration Read Type 0
{2'b10, 5'b0_0100}: Configuration Write Type 0
{2'b00, 5'b0_0101}: Configuration Read Type 1
{2'b10, 5'b0_0101}: Configuration Write Type 1
{2'b00, 5'b1_1011}: Trusted Configuration Read
{2'b10, 5'b1_1011}: Trusted Configuration Write
{2'b00, 5'b0_1010}: Completion without Data
{2'b10, 5'b0_1010}: Completion with Data
{2'b00, 5'b0_1011}: Completion without Data Locked
{2'b10, 5'b0_1011}: Completion with Data Locked
{2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe*
spec.)
{2'b11, 5'b1_0r2r1r0}: Message with Data
{2'b10, 5'b0_1100}: FetchAdd
{2'b11, 5'b0_1100}: FetchAdd
{2'b10, 5'b0_1101}: Swap
{2'b11, 5'b0_1101}: Swap
{2'b10, 5'b0_1110}: CAS
{2'b11, 5'b0_1110}: CAS
{2'b11, 5'b1_0r2r1r0}: Message with Data
{2'b10, 5'b0_1100}: FetchAdd
{2'b11, 5'b0_1100}: FetchAdd
{2'b10, 5'b0_1101}: Swap
{2'b11, 5'b0_1101}: Swap
{2'b10, 5'b0_1110}: CAS
{2'b11, 5'b0_1110}: CAS
4:0
ROS_V
0x0
Type[4:0]:
Type.
This field combined with the Format field specifies the transaction type.
This field combined with the Format field specifies the transaction type.
See the encodings in the description for the Fmt[1:0] field.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:2
Offset:
IRPP0: 0x240,
Size: 128 bits
IRPP1: 0x2c0
Bit
Attr
Default
Description