STMicroelectronics M41T81SMY6F Linear IC M41T81SMY6F Fiche De Données

Doc ID 10773 Rev 7

In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is 
shown in 

. Following the START condition and slave address, a logic '0' 

(R/W=0) is placed on the bus and indicates to the addressed device that word address “An” 
will follow and is to be written to the on-chip address pointer. The data word to be written to 
the memory is strobed in next and the internal address pointer is incremented to the next 
address location on the reception of an acknowledge clock. The M41T81S slave receiver 
will send an acknowledge clock to the master transmitter after it has received the slave 
address see 

 and again after it has received the word address and each 

data byte.

With valid V

CC

 applied, the M41T81S can be accessed as described above with READ or 

WRITE cycles. Should the supply voltage decay, the power input will be switched from the 
V

CC

 pin to the battery when V

CC

 falls below the battery backup switchover voltage (V

SO

). At 

this time the clock registers will be maintained by the attached battery supply. On power-up, 
when V

CC

 returns to a nominal value, write protection continues for t

REC

.

For a further, more detailed review of lifetime calculations, please see application note 
AN1012.

AI00591

BUS ACTIVITY:

AC

K

S

AC

K

AC

K

AC

K

AC

K

ST

OP

ST

AR

T

P

SDA LINE

BUS ACTIVITY:
MASTER

R/W

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS