STMicroelectronics M41T81SMY6F Linear IC M41T81SMY6F Fiche De Données
Codes de produits
M41T81SMY6F
Clock operation
M41T81S
Doc ID 10773 Rev 7
Output driver pin
When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
calibration register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location
08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
calibration register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location
08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
Note:
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state:
watchdog register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1' state:
ST; OUT; OF; and HT (see
watchdog register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1' state:
ST; OUT; OF; and HT (see
Table 5.
Preferred default values
Condition
ST
HT
Out
FT
AFE SQWE
ABE
WATCHDOG
register
(1)
OF
OFIE
Initial power-up
(2)
1
1
1
0
0
0
0
0
1
0
Subsequent power-up
(with battery backup)
(with battery backup)
(3)
UC
1
UC
0
UC
UC
UC
0
UC
UC
1.
BMB0-BMB4, RB0, RB1
2.
State of other control bits undefined
3.
UC = Unchanged