Texas Instruments Delfino C28346 DIM168 ControlCARD TMDSCNCD28346-168 TMDSCNCD28346-168 Fiche De Données
Codes de produits
TMDSCNCD28346-168
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.14.2 SPI Slave Mode Timing
lists the slave mode external timing (clock phase = 0) and
(clock phase = 1).
and
show the timing waveforms.
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)
(1) (2) (3) (4) (5)
NO.
MIN
MAX
UNIT
12
t
c(SPC)S
Cycle time, SPICLK
4t
c(LCO)
ns
13
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
ns
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
14
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
15
t
d(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
20
ns
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
20
16
t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
0.75t
c(SPC)S
ns
(clock polarity = 0)
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
0.75t
c(SPC)S
(clock polarity = 1)
19
t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
20
ns
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
20
20
t
v(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
0.5t
c(SPC)S
– 10
ns
(clock polarity = 0)
t
v(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
0.5t
c(SPC)S
– 10
(clock polarity = 1)
(1)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2)
t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX.
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX.
(4)
t
c(LCO)
= LSPCLK cycle time
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Copyright © 2009–2012, Texas Instruments Incorporated
Electrical Specifications
137
Product Folder Link(s):