Texas Instruments Delfino C28346 DIM168 ControlCARD TMDSCNCD28346-168 TMDSCNCD28346-168 Fiche De Données
Codes de produits
TMDSCNCD28346-168
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.15.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements
MIN
MAX
UNIT
t
a(A)
Access time, read data from address valid
(LR + AR) – 13.5
(1)
ns
t
a(XRD)
Access time, read data valid from XRD active low
AR – 13
(1)
ns
t
su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
13
ns
t
h(XD)XRD
Hold time, read data valid after XRD inactive high
0
ns
(1)
LR = Lead period, read access. AR = Active period, read access. See
.
Table 6-38. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
0
2
ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
– 0.2
0.9
ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid
1.5
ns
t
d(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
–0.2
0.8
ns
t
d(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high
– 0.4
0.8
ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
t
h(XA)XRD
Hold time, address valid after XRD inactive high
(1)
ns
(1)
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Copyright © 2009–2012, Texas Instruments Incorporated
Electrical Specifications
145
Product Folder Link(s):