Texas Instruments Delfino C28346 DIM168 ControlCARD TMDSCNCD28346-168 TMDSCNCD28346-168 Fiche De Données
Codes de produits
TMDSCNCD28346-168
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
2.2
Signal Descriptions
describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available
in all devices. See
in all devices. See
for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength
of 4 mA (typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be
selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups
on GPIO0–GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57
and GPIO64–GPIO87 are enabled upon reset.
selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups
on GPIO0–GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57
and GPIO64–GPIO87 are enabled upon reset.
Table 2-2. Signal Descriptions
ZHH
ZFE
NAME
DESCRIPTION
BALL #
BALL #
JTAG
M7
R8
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
TRST
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k
Ω
resistor generally offers adequate protection. Since this is application-specific, it is recommended
that each target board be validated for proper operation of the debugger and the application. (I,
that each target board be validated for proper operation of the debugger and the application. (I,
↓
)
P9
T11
JTAG test clock. An external pullup resistor is required on this pin. A 2.2-k
Ω
resistor generally offers
TCK
adequate protection.(I)
M8
P9
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
TMS
controller on the rising edge of TCK. (I,
↑
)
L6
T8
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
TDI
or data) on a rising edge of TCK. (I,
↑
)
N7
P8
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
TDO
are shifted out of TDO on the falling edge of TCK.
N9
P10
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
EMU0
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
Ω
to 4.7-k
Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
board be validated for proper operation of the debugger and the application.
L9
R10
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
EMU1
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
Ω
to 4.7-k
Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
board be validated for proper operation of the debugger and the application.
Clock
B14
D16
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
XCLKOUT
At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-
impedance state during a reset.
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-
impedance state during a reset.
D9
A12
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
XCLKIN
the X1 pin must be tied to V
SSK
. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to V
SS
. (I)
C8
A7
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
X1
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to V
SS
.
If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to V
SSK
. (I)
A8
A9
Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it
X2
must be left unconnected. (O)
Copyright © 2009–2012, Texas Instruments Incorporated
Introduction
23
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