Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 Fiche De Données
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TMDSCNCD28M36
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.16.2 GPIO_MUX2
The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight
General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each
GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are
configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed
through a separate set of registers from those used to program GPIO_MUX1.
General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each
GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are
configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed
through a separate set of registers from those used to program GPIO_MUX1.
The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G.
They are accessible by the C28x CPU only. The middle portion of
They are accessible by the C28x CPU only. The middle portion of
shows set G of Control
Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register
selects one of six possible digital output signals from analog comparators, or one of eight general-purpose
GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a
corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the
eight GPIO bits, as well as setting the direction for each of the bits (read or write). See
selects one of six possible digital output signals from analog comparators, or one of eight general-purpose
GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a
corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the
eight GPIO bits, as well as setting the direction for each of the bits (read or write). See
for the
mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2.
Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to “00”,
“01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00”
(Peripheral Mode 0) assigns pin GPIO194 to internal signal GPIO194 (digital GPIO). Setting bits 5–4 of
the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO194 to internal signal COMP6OUT
coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently
available.
“01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00”
(Peripheral Mode 0) assigns pin GPIO194 to internal signal GPIO194 (digital GPIO). Setting bits 5–4 of
the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO194 to internal signal COMP6OUT
coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently
available.
Table 3-31. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)
(1)
C28x
C28x
C28x
C28x
Device Pin Name
Peripheral
Peripheral
Peripheral
Peripheral
Mode 0
Mode 1
Mode 2
Mode 3
GPIO192
GPIO192
–
–
–
GPIO193
GPIO193
–
–
COMP1OUT
GPIO194
GPIO194
–
–
COMP6OUT
GPIO195
GPIO195
–
–
COMP2OUT
GPIO196
GPIO196
–
–
COMP3OUT
GPIO197
GPIO197
–
–
COMP4OUT
GPIO198
GPIO198
–
–
–
GPIO199
GPIO199
–
–
COMP5OUT
(1)
Blank fields represent Reserved functions.
Copyright © 2012–2014, Texas Instruments Incorporated
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