Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Fiche De Données
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Codes de produits
DK-TM4C129X
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate
SS
bits should be set along with the
SYNCWAIT
bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate
ADC module is configured, its ADCPSSI register should be written with the appropriate
SS
bits set
along with the
GSYNC
bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type RW, reset -
ADC1 base: 0x4003.9000
Offset 0x028
Type RW, reset -
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
SYNCWAIT
reserved
GSYNC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
RO
RO
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SS0
SS1
SS2
SS3
reserved
WO
WO
WO
WO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Global Synchronize
Description
Value
This bit is cleared once sampling has been initiated.
0
This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
time. Any ADC module that has been initialized by setting an
SSn
bit and the
SYNCWAIT
bit starts sampling once this bit is
written.
1
0
RW
GSYNC
31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
30:28
Synchronize Wait
Description
Value
Sampling begins when a sample sequence has been initiated.
0
This bit allows the sample sequences to be initiated, but delays
sampling until the
sampling until the
GSYNC
bit is set.
1
0
RW
SYNCWAIT
27
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0
RO
reserved
26:4
1251
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller