Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U Fiche De Données
Codes de produits
PCM5142EVM-U
C
P
V
D
D
C
A
P
P
C
P
G
N
D
C
A
P
M
V
N
E
G
O
U
T
L
O
U
T
R
A
V
D
D
A
G
N
D
D
E
M
P
A
T
T
2
A
T
T
1
A
T
T
0
M
A
S
T
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
D
V
D
D
D
G
N
D
L
D
O
O
X
S
M
T
F
M
T
L
R
C
K
D
IN
B
C
K
S
C
K
F
L
T
M
O
D
E
2
M
O
D
E
1
D
O
U
T
A
G
N
S
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
PCM514x pin assignments-3 MODE1 tied DGND and MODE2 tied DGND : Hardwired mode
PCM514x (top view)
The H/W mode has digital gain and attenuation level control by decoding external ATT2 (11 pin), ATT1 (12 pin),
and ATT0 (pin 13). Table 1 shows the pins used to set gain and attenuation levels.
and ATT0 (pin 13). Table 1 shows the pins used to set gain and attenuation levels.
Table 4. Gain and Attenuation in Hardware Mode
ATT pin condition (ATT2 : ATT1 :
Gain and Attenuation level
ATT0)
( 0 0 0 )
0 dB
( 0 0 1 )
+ 3 dB
( 0 1 0 )
+ 6 dB
( 0 1 1 )
+ 9 dB
( 1 0 0 )
+ 12 dB
( 1 0 1 )
+ 15 dB
( 1 1 0 )
- 6 dB
( 1 1 1 )
- 3 dB
Table 5. PCM514x Hardwired mode Terminal Functions
Terminal
I/O
Description
Name
Pin
CPVDD
1
-
Charge pump power supply, 3.3V
CAPP
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
-
Charge pump ground
CAPM
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
O
Negative charge pump rail terminal for decoupling, -3.3V
OUTL
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
AVDD
8
-
Analog power supply, 3.3V
AGND
9
-
Analog ground
DEMP
10
I
De-emphasis control for 44.1kHz sampling rate
(1)
: Off (Low) / On (High)
ATT2
11
I
Digital gain and attenuation control pin
(1)
ATT1
12
I
Digital gain and attenuation control pin
(1)
ATT0
13
I
Digital gain and attenuation control pin
I
2
S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK
MAST
14
I
inputs
AGNS
15
I
Analog gain selector : 0dB 2V
RMS
output (Low), -6dB 1V
RMS
output (High)
GPO
16
O
General Purpose Output (Low level)
(1)
Failsafe LVCMOS Schmitt trigger input.
6
Copyright © 2012, Texas Instruments Incorporated
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