Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U Fiche De Données
Codes de produits
PCM5142EVM-U
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= 25°C, AV
DD
= CPV
DD
= DV
DD
= 3.3V, f
S
= 48kHz, system clock = 512f
S
and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
16
24
32
Bits
Data Format (PCM Mode)
Audio data interface format
I
2
S, left justified, right justified and TDM
Audio data bit length
16, 24, 32-bit acceptable
Audio data format
MSB First, 2s Complement
f
S
(1)
Sampling frequency
8
384
kHz
Clocks
System clock frequency
64, 128, 192, 256, 384, 512, 768, 1024, 1152,
1536, 2048, or 3072
f
1536, 2048, or 3072
f
SCK
, up to 50Mhz
Clock divider uses fractional divide
6.7
20
MHz
D > 0, P=1
PLL Input Frequency
(SCL Clock Frequency 400 kHz)
(SCL Clock Frequency 400 kHz)
Clock divider uses integer divide
1
20
MHz
D = 0, P=1
Digital Input/Output
Logic Family: 3.3V LVCMOS compatible
V
IH
0.7×DV
DD
Input logic level
V
V
IL
0.3×DV
DD
I
IH
V
IN
= V
DD
10
Input logic current
µA
I
IL
V
IN
= 0V
–10
V
OH
I
OH
= –4mA
0.8×DV
DD
Output logic level
V
V
OL
I
OL
= 4mA
0.22×DV
D
D
Logic Family 1.8V LVCMOS compatible
V
IH
0.7×DV
DD
Input logic level
V
V
IL
0.3×DV
DD
I
IH
V
IN
= V
DD
10
Input logic current
µA
I
IL
V
IN
= 0V
–10
V
OH
I
OH
= –2mA
0.8×DV
DD
Output logic level
V
V
OL
I
OL
= 2mA
0.22×DV
D
D
(1)
One sample time si defined as the reciprocal of the sampling frequency. 1t
S
= 1/f
S
Copyright © 2012, Texas Instruments Incorporated
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