Microchip Technology DV164136 Fiche De Données
PIC18F8722 FAMILY
DS39646C-page 136
© 2008 Microchip Technology Inc.
TABLE 11-1:
PORTA FUNCTIONS
TABLE 11-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0
RA0
0
O
DIG
LATA<0> data output; not affected by analog input.
1
I
TTL
PORTA<0> data input; disabled when analog input enabled.
AN0
1
I
ANA
A/D input channel 0. Default input configuration on POR; does not affect
digital output.
digital output.
RA1/AN1
RA1
0
O
DIG
LATA<1> data output; not affected by analog input.
1
I
TTL
PORTA<1> data input; disabled when analog input enabled.
AN1
1
I
ANA
A/D input channel 1. Default input configuration on POR; does not affect
digital output.
digital output.
RA2/AN2/V
REF
-
RA2
0
O
DIG
LATA<2> data output; not affected by analog input.
1
I
TTL
PORTA<2> data input. Disabled when analog functions enabled.
AN2
1
I
ANA
A/D input channel 2. Default input configuration on POR.
V
REF
-
1
I
ANA
Comparator voltage reference low input and A/D voltage reference low input.
RA3/AN3/V
REF
+
RA3
0
O
DIG
LATA<3> data output; not affected by analog input.
1
I
TTL
PORTA<3> data input; disabled when analog input enabled.
AN3
1
I
ANA
A/D input channel 3. Default input configuration on POR.
V
REF
+
1
I
ANA
Comparator voltage reference high input and A/D voltage reference
high input.
high input.
RA4/T0CKI
RA4
0
O
DIG
LATA<4> data output.
1
I
ST
PORTA<4> data input; default configuration on POR.
T0CKI
x
I
ST
Timer0 clock input.
RA5/AN4/HLVDIN
RA5
0
O
DIG
LATA<5> data output; not affected by analog input.
1
I
TTL
PORTA<5> data input; disabled when analog input enabled.
AN4
1
I
ANA
A/D input channel 4. Default configuration on POR.
HLVDIN
1
I
ANA
High/Low-Voltage Detect external trip point input.
OSC2/CLKO/RA6
OSC2
x
O
ANA
Main oscillator feedback output connection (XT, HS, HSPLL and LP modes).
CLKO
x
O
DIG
System cycle clock output (F
OSC
/4) in all oscillator modes except RC,
INTIO7 and EC.
RA6
0
O
DIG
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1
I
TTL
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC1/CLKI/RA7
OSC1
x
I
ANA
Main oscillator input connection.
CLKI
x
I
ANA
Main clock input connection.
RA7
0
O
DIG
LATA<7> data output. Disabled in external oscillator modes.
1
I
TTL
PORTA<7> data input. Disabled in external oscillator modes.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTA
RA7
(1)
RA6
(1)
RA5
RA4
RA3
RA2
RA1
RA0
LATA
LATA7
(1)
LATA6
(1)
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
TRISA
TRISA7
(1)
TRISA6
(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
configuration; otherwise, they are read as ‘0’.