Microchip Technology DV164136 Fiche De Données
PIC18F8722 FAMILY
DS39646C-page 266
© 2008 Microchip Technology Inc.
20.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>), or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>), or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
setting bits, SYNC, SPEN and CSRC.
3.
Ensure bits, CREN and SREN, are clear.
4.
If interrupts are desired, set enable bit, RCxIE.
5.
If 9-bit reception is desired, set bit, RX9.
6.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
For continuous reception, set bit, CREN.
7.
Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
8.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREGx register.
RCREGx register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 20-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
DTx pin
CKx pin
Write to
bit SREN
SREN bit
RCxIF bit
(Interrupt)
Read
RCREGx
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1 Q2 Q3 Q4
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
CKx pin
(SCKP = 0)
(SCKP = 1)