Microchip Technology MA330031-2 Fiche De Données
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2011-2013 Microchip Technology Inc.
DS70000657H-page 257
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 2
HOMIEN:
Home Input Event Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 1
IDXIRQ:
Status Flag for Index Event Status bit
1
= Index event has occurred
0
= No Index event has occurred
bit 0
IDXIEN:
Index Input Event Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
REGISTER 17-3:
QEI1STAT: QEI1 STATUS REGISTER (CONTINUED)
Note 1:
This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.