Microchip Technology MCP1630DM-DDBS1 Fiche De Données
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2007 Microchip Technology Inc.
DS41211D-page 55
PIC12F683
8.6
Comparator Interrupt Operation
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Changes are recognized by means of a mismatch cir-
cuit which consists of two latches and an exclusive-or
gate (see Figure 8.2). One latch is updated with the
comparator output level when the CMCON0 register is
read. This latch retains the value until the next read of
the CMCON0 register or the occurrence of a Reset.
The other latch of the mismatch circuit is updated on
every Q1 system clock. A mismatch condition will occur
when a comparator output change is clocked through
the second latch on the Q1 clock cycle. The mismatch
condition will persist, holding the CMIF bit of the PIR1
register true, until either the CMCON0 register is read
or the comparator output returns to the previous state.
a change in the output value of the comparator.
Changes are recognized by means of a mismatch cir-
cuit which consists of two latches and an exclusive-or
gate (see Figure 8.2). One latch is updated with the
comparator output level when the CMCON0 register is
read. This latch retains the value until the next read of
the CMCON0 register or the occurrence of a Reset.
The other latch of the mismatch circuit is updated on
every Q1 system clock. A mismatch condition will occur
when a comparator output change is clocked through
the second latch on the Q1 clock cycle. The mismatch
condition will persist, holding the CMIF bit of the PIR1
register true, until either the CMCON0 register is read
or the comparator output returns to the previous state.
Software will need to maintain information about the
status of the comparator output to determine the actual
change that has occurred.
status of the comparator output to determine the actual
change that has occurred.
The CMIF bit of the PIR1 register, is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘
interrupt flag. This bit must be reset in software by
clearing it to ‘
0
’. Since it is also possible to write a ‘
1
’ to
this register, a simulated interrupt may be initiated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
interrupt in the following manner:
a)
Any read or write of CMCON0. This will end the
mismatch condition.
mismatch condition.
b)
Clear the CMIF interrupt flag.
A persistent mismatch condition will preclude clearing
the CMIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CMIF bit to be
cleared.
the CMIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CMIF bit to be
cleared.
FIGURE 8-5:
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
INTERRUPT TIMING W/O
CMCON0 READ
FIGURE 8-6:
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
INTERRUPT TIMING WITH
CMCON0 READ
Note:
A write operation to the CMCON0 register
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
Note:
If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF interrupt flag
may not get set.
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF interrupt flag
may not get set.
Note 1: If a change in the CMCON0 register
(COUT) should occur when a read opera-
tion is being executed (start of the Q2
cycle), then the CMIF of the PIR1 register
interrupt flag may not get set.
tion is being executed (start of the Q2
cycle), then the CMIF of the PIR1 register
interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1
μ
s for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CIN+
COUT
Set CMIF (level)
CMIF
T
RT
reset by software
Q1
Q3
CIN+
COUT
Set CMIF (level)
CMIF
T
RT
reset by software
cleared by CMCON0 read