STMicroelectronics M93C66-WMN6P Memory IC M93C66-WMN6P Fiche De Données
Codes de produits
M93C66-WMN6P
Instructions
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x
DocID4997 Rev 15
5.2.4
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in
.
Figure 7. ERASE, ERAL sequences
1. For the meanings of An and Xn, please see
and
5.2.5 Erase
All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in
.
AI00879B
S
ERASE
1 1
D
Q
ADDR
OP
CODE
1
BUSY
READY
CHECK
STATUS
S
ERASE
ALL
ALL
1
0
D
Q
OP
CODE
1
BUSY
READY
CHECK
STATUS
0
0
An
A0
Xn X0
ADDR