Microchip Technology DM240015 Fiche De Données
PIC24FJ128GC010 FAMILY
DS30009312B-page 344
2012-2013 Microchip Technology Inc.
REGISTER 25-1:
BUFCON0: INTERNAL VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
BUFEN
—
BUFSIDL
BUFSLP
—
—
—
—
bit 15
bit 8
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
BUFSTBY
—
—
—
—
BUFREF1
BUFREF0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
BUFEN:
Enable Buffer V
REF
Source bit
1
= Band gap and buffer are enabled
0
= Band gap and buffer are disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
BUFSIDL:
Buffer Stop in Idle bit
1
= Buffer is disabled in Idle mode
0
= Buffer works normally in Idle mode
bit 12
BUFSLP:
Buffer Sleep Enable bit
1
= Buffer is disabled in Sleep mode
0
= Buffer works normally in Sleep mode
bit 11-7
Unimplemented:
Read as ‘0’
bit 6
BUFSTBY:
Buffer Standby Enable bit
1
= Buffer in Low-Power Standby mode (output unknown or weak drive strength; allows quicker
start-up than clearing BUFEN)
0
= Buffer output works normally
bit 5-2
Unimplemented:
Read as ‘0’
bit 1-0
BUFREF<1:0>:
Internal Voltage Reference Select bits
11
= Reference output set at 3.072V
10
= Reference output set at 2.560V
01
= Reference output set at 2.048V
00
= Reference output set at 1.2V
Note 1:
The BGBUF cannot “boost” the AV
DD
voltage to a higher level. Therefore, BUFREF<1:0> bits settings
higher than the applied AV
DD
level are considered invalid.