STMicroelectronics M48Z12-150PC1 Memory IC M48Z12-150PC1 Fiche De Données
Codes de produits
M48Z12-150PC1
M48Z02, M48Z12
Operation modes
Doc ID 2420 Rev 9
7/22
2 Operation
modes
The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
monitors the single 5 V supply for an out of tolerance condition. When V
CC
is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below
approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.
until valid power returns.
Table 2.
Operating modes
Note:
X = V
IH
or V
IL
; V
SO
= battery backup switchover voltage.
2.1 READ
mode
The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
AVQV
) after the last
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
ELQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
for output data hold time (t
AXQX
) but will go indeterminate until the next address access.
Mode
V
CC
E
G
W
DQ0-
DQ7
Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
V
IH
X
X
High Z
Standby
WRITE
V
IL
X
V
IL
D
IN
Active
READ
V
IL
V
IL
V
IH
D
OUT
Active
READ
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(1)
1.
See
for details.
X
X
X
High Z
CMOS standby
Deselect
≤ V
SO
X
X
X
High Z
Battery backup mode