Microchip Technology MA330012 Fiche De Données
dsPIC33F
DS70165E-page 140
Preliminary
©
2007 Microchip Technology Inc.
REGISTER 7-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
—
AMODE<1:0>
—
—
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHEN: Channel Enable bit
1
= Channel enabled
0
= Channel disabled
bit 14
SIZE: Data Transfer Size bit
1
= Byte
0
= Word
bit 13
DIR: Transfer Direction bit (source/destination bus select)
1
= Read from DMA RAM address, write to peripheral address
0
= Read from peripheral address, write to DMA RAM address
bit 12
HALF: Early Block Transfer Complete Interrupt Select bit
1
= Initiate block transfer complete interrupt when half of the data has been moved
0
= Initiate block transfer complete interrupt when all of the data has been moved
bit 11
NULLW: Null Data Peripheral Write Mode Select bit
1
= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0
= Normal operation
bit 10-6
Unimplemented: Read as ‘
0
’
bit 5-4
AMODE<1:0>: DMA Channel Operating Mode Select bits
11
= Reserved (will act as Peripheral Indirect Addressing mode)
10
= Peripheral Indirect Addressing mode
01
= Register Indirect without Post-Increment mode
00
= Register Indirect with Post-Increment mode
bit 3-2
Unimplemented: Read as ‘
0
’
bit 1-0
MODE<1:0>: DMA Channel Operating Mode Select bits
11
= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10
= Continuous, Ping-Pong modes enabled
01
= One-Shot, Ping-Pong modes disabled
00
= Continuous, Ping-Pong modes disabled