Microchip Technology AC244045 Fiche De Données
© 2009 Microchip Technology Inc.
DS41341E-page 25
PIC16F72X/PIC16LF72X
Bank 1
80h
(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h
(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
83h
(2)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
84h
(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
88h
(3)
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
89h
TRISE
—
—
—
—
TRISE3
(6)
TRISE2
(3)
TRISE1
(3)
TRISE0
(3)
---- 1111
8Ah
(1, 2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh
(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
8Ch
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq
8Fh
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
90h
OSCCON
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
--10 qq--
91h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
(5)
Synchronous Serial Port (I
2
C
™
mode) Address Register
0000 0000
93h
SSPMSK
(4)
Synchronous Serial Port (I
2
C
™
mode) Address Mask Register
1111 1111
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
95h
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
96h
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
9Dh
FVRCON
FVRRDY
FVREN
—
—
—
—
ADFVR1
ADFVR0
q0-- --00
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
—
ADCS2
ADCS1
ADCS0
—
—
ADREF1
ADREF0
0000 --00
TABLE 2-1:
PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
4:
Accessible only when SSPM<3:0> = 1001.
5:
Accessible only when SSPM<3:0>
≠ 1001.
6:
This bit is always ‘1’ as RE3 is input only.