Microchip Technology MA330024 Fiche De Données
2009-2014 Microchip Technology Inc.
DS70000591F-page 443
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Section 9.0 “Oscillator Configuration” Removed Section 9.2 “FRC Tuning”.
Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator
Control Register (see Register 9-1).
Control Register (see Register 9-1).
Updated the Oscillator Tuning Register (see Register 9-4).
Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift
Register.
Register.
Updated the default Reset values from R/W-0 to R/W-1 for the SELACLK
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 9-5).
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 9-5).
Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see
Register 9-6).
Register 9-6).
Section 10.0 “Power-Saving Features” Updated the last paragraph of Section 10.2.2 “Idle Mode” to clarify when
instruction execution begins.
Added Note 1 to the PMD1 register (see Register 10-1).
Section 11.0 “I/O Ports”
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
second paragraph of Section 11.2 “Open-Drain Configuration”.
Section 16.0 “High-Speed PWM”
Updated the High-Speed PWM Module Register Interconnect Diagram
(see Figure 16-2).
(see Figure 16-2).
Updated the SYNCSRC<2:0> = 111, 101, and 100 definitions to
Reserved in the PTCON and STCON registers (see Register 16-1 and
Register 16-5).
Reserved in the PTCON and STCON registers (see Register 16-1 and
Register 16-5).
Updated the PWM time base maximum value from 0xFFFB to 0xFFF8 in
the PTPER register (Register 16-3).
the PTPER register (Register 16-3).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1
of the shaded note that follows the MDC register (see Register 16-10).
of the shaded note that follows the MDC register (see Register 16-10).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 2
of the shaded note that follows the PDCx and SDCx registers (see
Register 16-12 and Register 16-13).
of the shaded note that follows the PDCx and SDCx registers (see
Register 16-12 and Register 16-13).
Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits,
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 16-19).
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 16-19).
Section 20.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Asynchronous Receiver Transmitter
(UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at 40
MIPS.
MIPS.
Section 22.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)”
Analog-to-Digital Converter (ADC)”
Updated the TRGSRCx<4:0> = 01101 definition from Reserved to PWM
secondary special event trigger selected, and updated Note 1 in the
ADCP0-ADCP6 registers (see Register 22-6 through Register 22-12).
secondary special event trigger selected, and updated Note 1 in the
ADCP0-ADCP6 registers (see Register 22-6 through Register 22-12).
Section 24.0 “Special Features”
Updated the second paragraph and removed the fourth paragraph in
Section 24.1 “Configuration Bits”.
Section 24.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 24-1).
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description