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Intel Core™ 2 Duo U7600 U7600 Manuel D’Utilisation

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U7600
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Page de 42
 
Errata 
 
 
18
  
 Specification 
Update 
AZ2. 
INVLPG Operation for Large (2M/4M) Pages May Be Incomplete 
under Certain Conditions 
Problem: 
The INVLPG instruction may not completely invalidate Translation Look-aside Buffer 
(TLB) entries for large pages (2M/4M) when both of the following conditions exist: 
“Address range of the page being invalidated spans several Memory Type Range 
Registers (MTRRs) with different memory types specified (INVLPG operation is 
preceded by a Page Assist Event (Page Fault (#PF) or an access that results in either 
A or D bits being set in a Page Table Entry (PTE))  
Implication:  Stale translations may remain valid in TLB after a PTE update resulting in 
unpredictable system behavior. Intel has not observed this erratum with any 
commercially-available software. 
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for 
the entire address range of the large page. 
Status: 
For the steppings affected, see the Summary Tables of Changes. 
AZ3. 
Store to WT Memory Data May Be Seen in Wrong Order by Two, 
Subsequent Loads 
Problem: 
When data of Store to WT memory is used by two, subsequent loads of one thread, 
and another thread performs cacheable write to the same address, the first load may 
get the data from external memory or L2 written by another core, while the second 
load will get the data straight from the WT Store. 
Implication:  Software that uses WB to WT memory aliasing may violate proper store ordering. 
Workaround: Do not use WB to WT aliasing. 
Status: 
For the steppings affected, see the Summary Tables of Changes. 
AZ4. 
Non-Temporal Data Store May Be Observed in Wrong Program Order  
Problem: 
When non-temporal data is accessed by multiple read operations in one thread while 
another thread performs a cacheable write operation to the same address, the data 
stored may be observed in wrong program order (i.e., later load operations may read 
older data). 
Implication:  Software that uses non-temporal data without proper serialization before accessing 
the non-temporal data may observe data in wrong program order.  
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's 
Manual, Volume 3A, “Buffering of Write Combining Memory Locations” section will 
operate correctly. 
Status: 
For the steppings affected, see the Summary Tables of Changes.