Microchip Technology DM164134 Fiche De Données
PIC18FXX8
DS41159E-page 104
© 2006 Microchip Technology Inc.
9.5
PORTE, TRISE and LATE
Registers
Registers
PORTE is a 3-bit wide, bidirectional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
read and write the latched output value for PORTE.
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corre-
sponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corre-
sponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
The TRISE register also controls the operation of the
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
refer to Section 10.0 “Parallel Slave Port”.
function as its control inputs. For additional details,
refer to Section 10.0 “Parallel Slave Port”.
PORTE pins are also multiplexed with inputs for the A/D
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE<2:0> control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE<2:0> control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
EXAMPLE 9-5:
INITIALIZING PORTE
FIGURE 9-10:
PORTE BLOCK DIAGRAM
Note:
This port is only available on the
PIC18F448 and PIC18F458.
PIC18F448 and PIC18F458.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
03h
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE1:RE0 as inputs
; RE2 as an output
; (RE4=0 - PSPMODE Off)
Peripheral Out Select
Data Bus
WR LATE
WR TRISE
Data
Latch
TRIS Latch
RD TRISE
Q
D
Q
CK
Q
D
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
V
DD
V
SS
RD PORTE
Peripheral Data In
I/O pin
(1)
or
WR PORTE
WR PORTE
RD LATE
Schmitt
Trigger
Trigger
Note
1: I/O pins have diode protection to V
DD
and V
SS
.
TRIS OVERRIDE
Pin
Override Peripheral
RE0
Yes
PSP
RE1
Yes
PSP
RE2
Yes
PSP
TRIS
Override
Peripheral Enable