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PIC18FXX8
DS41159E-page 160
© 2006 Microchip Technology Inc.
FIGURE 17-10:
I
2
C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) 
SDA
SCL
SS
PI
BF
 (
S
SPS
T
A
T
<
0
>
)
S
1
2
3
4
5
6
7
8
9
1
23
4
5
67
8
9
1
2
34
5
7
8
9
P
1
1
1
1
0
A
9
A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Re
ce
iv
e
 Da
ta
 Byte
ACK
R/W
 = 
0
ACK
Re
ceive F
ir
s
t B
y
te of A
d
d
ress
C
lea
re
d i
n
 s
o
ft
w
a
re
D2
6
(P
IR
1<
3>
C
lear
ed i
n
 so
ftw
are
R
e
ce
iv
e
 S
e
cond B
y
te 
of A
ddre
s
s
C
le
a
red
 by har
dw
are
w
h
en S
S
P
A
D
D
 i
s
 update
d
w
ith
 l
o
w
 byte 
of add
ress
UA (
S
S
PST
A
T
<1
>)
Cl
o
ck is h
e
ld
 lo
w u
n
til
updat
e of S
S
P
A
D
D
 has 
ta
ken pl
a
c
e
UA
 is 
set indicat
in
g
 tha
t
the S
S
P
A
D
D
 need
s to be
upda
ted
U
A
 i
s
 set 
in
di
cati
ng 
that
S
S
P
A
D
D
 need
s to be
u
pdate
d
C
le
a
red 
by har
dw
are
 w
hen
S
S
P
A
D
D
 i
s
 upda
ted w
it
hi
gh
b
y
te of 
addr
ess
S
SPB
UF
 is wr
itte
n
 wi
th
conten
ts o
f S
S
P
S
R
D
u
mmy 
read
 of S
S
P
B
U
F
to clear
 B
F
 flag
AC
K
CKP
12
3
4
5
7
89
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
 Da
ta
 B
y
te
B
u
s m
a
ste
r
term
inates
tran
sfer
D2
6
ACK
Cle
a
re
d
 in
 so
ft
wa
re
Cle
a
re
d
 in
 so
ft
w
a
re
SSP
O
V
 (
S
SPCO
N
1
<
6
>
)
S
SPO
V
 is
 s
e
t
because
 S
S
P
B
U
F
 i
s
stil
l f
u
ll. AC
K
 i
s
 no
t sent.
(C
K
P
 do
es not 
reset 
to ‘
0
’ w
hen 
S
E
N
 =
 0
)
Clo
ck is h
e
ld
 lo
w u
n
til
upda
te of 
S
S
P
A
D
D
 has 
ta
k
e
n
 pl
ac
e