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PIC18FXX8
DS41159E-page 30
© 2006 Microchip Technology Inc.
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
PIC18F2X8 PIC18F4X8
---0 0000
---0 0000
---0 uuuu
(3)
TOSH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
(3)
TOSL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
(3)
STKPTR
PIC18F2X8 PIC18F4X8
00-0 0000
uu-0 0000
uu-u uuuu
(3)
PCLATU
PIC18F2X8 PIC18F4X8
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
PC + 2
(2)
TBLPTRU
PIC18F2X8 PIC18F4X8
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F2X8 PIC18F4X8
0000 000x
0000 000u
uuuu uuuu
(1)
INTCON2
PIC18F2X8 PIC18F4X8
111- -1-1
111- -1-1
uuu- -u-u
(1)
INTCON3
PIC18F2X8 PIC18F4X8
11-0 0-00
11-0 0-00
uu-u u-uu
(1)
INDF0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTINC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTDEC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PREINC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PLUSW0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
FSR0H
PIC18F2X8 PIC18F4X8
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTINC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTDEC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PREINC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PLUSW1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
interrupt vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 3-2 for Reset value for specific condition.
5:
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
oscillator modes, they are disabled and read ‘0’.
6:
Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).