Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Fiche De Données
Codes de produits
MPC8309-KIT
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Overview
1
Overview
The MPC8309 incorporates the e300c3 (MPC 6 03e-based) core built on Power Architecture® technology,
which includes 16 KB of each L1 instruction and data caches, dual integer units, and on-chip memory
management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and
a 16/32-bit DDR2 memory controller with 8-bit ECC.
which includes 16 KB of each L1 instruction and data caches, dual integer units, and on-chip memory
management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and
a 16/32-bit DDR2 memory controller with 8-bit ECC.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.
capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.
Figure 1. MPC8309 block diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII
Ethernet, HDLC and TDM.
Ethernet, HDLC and TDM.
In summary, the MPC8309 provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
2 RMII/MII
2x TDM Ports
16-KB
D-Cache
16-KB
I-Cache
e300c3 Core with Power
2x DUART
Interrupt
I2C
Timers
GPIO
Enhanced
DDR2
Controller
Controller
Baud Rate
Generators
Accelerators
Single 32-bit RISC CP Serial DMA
Serial Interface
QUICC Engine™ Block
U
CC7
UCC5
UCC3
UCC2
UCC1
Time Slot Assigner
16 KB Multi-User RAM
FPU
Management
SPI
RTC
Local Bus
2x HDLC
1 RMII/MII
2x IEEE 1588
USB 2.0 HS
Host/Device/OTG
ULPI
4 FlexCAN
eSDHC
48 KB Instruction RAM
DMA
Engine 2
DMA
Engine 1
PCI Controller
IO
Sequencer