Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Fiche De Données
Codes de produits
MPC8309-KIT
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor
45
SPI
20.2
SPI AC timing specifications
The following table and provide the SPI input and output AC timing specifications.
The following figure
provides the AC test load for the SPI.
Figure 34. SPI AC test load
and
represent the AC timing from
. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
is the active edge.
Table 49. SPI DC electrical characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
V
OH
I
OH
= –6.0 mA
2.4
—
V
Output low voltage
V
OL
I
OL
= 6.0 mA
—
0.5
V
Output low voltage
V
OL
I
OL
= 3.2 mA
—
0.4
V
Input high voltage
V
IH
—
2.0
OV
DD
+ 0.3
V
Input low voltage
V
IL
—
–0.3
0.8
V
Input current
I
IN
0 V
≤ V
IN
≤ OV
DD
— ±
5
μA
Table 50. SPI AC timing specifications
1
Characteristic Symbol
2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
t
NIKHOV
0.5
6
ns
SPI outputs—Slave mode (external clock) delay
t
NEKHOV
2
8
ns
SPI inputs—Master mode (internal clock) input setup time
t
NIIVKH
6
—
ns
SPI inputs—Master mode (internal clock) input hold time
t
NIIXKH
0
—
ns
SPI inputs—Slave mode (external clock) input setup time
t
NEIVKH
4
—
ns
SPI inputs—Slave mode (external clock) input hold time
t
NEIXKH
2
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
NIKHOV
symbolizes the NMSI
outputs internal timing (NI) for the time t
SPI
memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
3. All units of output delay must be enabled for 8309_output_port spimosi_lpgl0(SPI Master mode)
4. Delay units must not be enabled for Slave mode.
4. Delay units must not be enabled for Slave mode.
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω