Analog Devices AD5061 Evaluation Board EVAL-AD5061EBZ EVAL-AD5061EBZ Fiche De Données
Codes de produits
EVAL-AD5061EBZ
EVAL-AD5040EB/EVAL-AD506xEB
Rev. 0 | Page 3 of 12
EVALUATION BOARD HARDWARE
The evaluation board for the AD5040/AD506x requires a single
positive supply (+2.7 V to +5.5 V). The evaluation board for the
AD5063 requires a single negative supply, such as −5 V, for the
external on-board op amp in order to generate a bipolar signal.
A +5 V
positive supply (+2.7 V to +5.5 V). The evaluation board for the
AD5063 requires a single negative supply, such as −5 V, for the
external on-board op amp in order to generate a bipolar signal.
A +5 V
DD
and −5 V
SS
supply are required to power the output
amplifier in the AD5063, if the user requires a bipolar signal.
The +5 V V
The +5 V V
DD
is used to power the DAC. All supplies are
decoupled to ground with 10 μF tantalum and 0.1 μF ceramic
capacitors.
capacitors.
EVALUATION BOARD LINK CONFIGURATON
The three link options (LK1, LK2, and LK3) must be set before
using the evaluation board.
using the evaluation board.
LK1
This sets the power to the Cypress USB microcontroller that
controls the USB section of the chip. The supply for the
microcontroller can be provided from an external supply or
from the computer via the USB interface. Using the computer to
set the supply, set Link 1 to Position A. To use an external
supply, set the link to Position B.
controls the USB section of the chip. The supply for the
microcontroller can be provided from an external supply or
from the computer via the USB interface. Using the computer to
set the supply, set Link 1 to Position A. To use an external
supply, set the link to Position B.
LK2
Link 2 connects the on chip reference to the Reference pin on
the DAC. If you are using the ADR423 to provide the reference
to the DAC, then Link 2 must be set.
the DAC. If you are using the ADR423 to provide the reference
to the DAC, then Link 2 must be set.
LK3
Link 3 is normally connected. This shows proper connection of
the USB chip.
the USB chip.
SETUP CONDITIONS
Care should be taken before applying power and signals to the
evaluation board to ensure that all link positions are as per the
required operating mode. Table 1 shows the position in which
all the links are set when the evaluation board is packaged.
evaluation board to ensure that all link positions are as per the
required operating mode. Table 1 shows the position in which
all the links are set when the evaluation board is packaged.
Table 1. Initial Link and Switch Positions
Link No.
Initial Position Function
LK1
Set to Position A Power supplied from computer.
LK2
Closed
Reference supplied to Reference
pin from ADR423.
pin from ADR423.
LK3 Closed
USB
cable
connected.
EVALUATION BOARD INTERFACING
The AD5040/AD5060/AD5061/AD5062 have 8 pins while the
AD5063 has 10 pins as described in Table 2. Note that the last
two entries in Table 2 (Pin INV and Pin R
AD5063 has 10 pins as described in Table 2. Note that the last
two entries in Table 2 (Pin INV and Pin R
FB
) apply only to the
AD5063. Communication to the devices is accomplished via the
Cypress CY7C63013 microcontroller Pin 45, Pin 46, and Pin 47.
Cypress CY7C63013 microcontroller Pin 45, Pin 46, and Pin 47.
Table 2. AD5040/AD506x Pin Configuration
Mnemonic Function
V
DD
Power supply input. Devices can operate from 2.7 V
to 5.5 V and V
to 5.5 V and V
DD,
and should be decoupled to GND.
V
REF
Reference voltage input.
DACGND
Ground input to the DAC.
V
OUT
Analog output voltage from DAC.
SYNC
Level triggered control input (active low). This is
the frame synchronization signal for the input
data. When SYNC goes low, it enables the input
shift register and data is transferred in on the
falling edges of the following clocks. The DAC is
updated following the 16
the frame synchronization signal for the input
data. When SYNC goes low, it enables the input
shift register and data is transferred in on the
falling edges of the following clocks. The DAC is
updated following the 16
th
clock cycle unless SYNC
is taken high before this edge in which case the
rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the DAC.
rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the DAC.
SCLK
Serial clock input. Data is clocked into the input
shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
D
IN
Serial data input. This device has a 16-/24-bit shift
register. Data is clocked into the register on the
falling edge of the serial clock input.
register. Data is clocked into the register on the
falling edge of the serial clock input.
AGND
Ground reference point for analog circuitry on part.
Connected to the internal scaling resistors of the
DAC. Connect the INV pin to the external op amp’s
inverting input in bipolar mode.
DAC. Connect the INV pin to the external op amp’s
inverting input in bipolar mode.
R
FB1
Feedback resistor. In bipolar mode, connect this
pin to the external op amp circuit.
pin to the external op amp circuit.
1
For AD5063 only.
SOCKETS
The J3 and J6 sockets are described in Table 3.
Table 3. Socket Functions
Socket
Function
J3
Subminiature BNC socket for the DAC output.
J6
Subminiature BNC socket for the reference output.
The evaluation board connectors are described in Table 4.
Table 4. Connector Function
Connector Functions
J1 USB
connector.
J2
PCB-mounting terminal block. Supplies the digital
power supply to the microcontroller.
power supply to the microcontroller.
J3, J6
PCB-mounting SMB connector. Provides
connection to on-board reference output voltage.
connection to on-board reference output voltage.
J4, J7
PCB-mounting terminal block. Provides the
reference power supply.
reference power supply.
J5
PCB-mounting terminal block. Provides the power
supply to the AD5040/AD506x.
supply to the AD5040/AD506x.
J9
PCB-mounting terminal block. Provides connection
to the DAC R
to the DAC R
FB
pin.
1
For AD5063 only.