Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ Fiche De Données
Codes de produits
AD9253-125EBZ
AD9253
Data Sheet
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
Temp
Min
Typ
Max
Unit
CLOCK
Input Clock Rate
Full
10
1000
MHz
Conversion Rate
Full
10
80/105/125
MSPS
Clock Pulse Width High (t
EH
) Full
6.25/4.76/4.00
ns
Clock Pulse Width Low (t
EL
) Full
6.25/4.76/4.00
ns
OUTPUT PARAMETERS
Propagation Delay (t
PD
)
Full
2.3
ns
Rise Time (t
R
) (20% to 80%)
Full
300
ps
Fall Time (t
F
) (20% to 80%)
Full
300
ps
FCO Propagation Delay (t
FCO
)
Full
1.5
2.3
3.1
ns
DCO Propagation Delay (t
Full
t
FCO
+ (t
SAMPLE
/16)
ns
DCO to Data Delay (t
DATA
Full
(t
SAMPLE
/16) − 300
(t
SAMPLE
/16) (t
SAMPLE
/16) + 300
ps
DCO to FCO Delay (t
FRAME
Full
(t
SAMPLE
/16) − 300
(t
SAMPLE
/16) (t
SAMPLE
/16) + 300
ps
Lane Delay (t
LD
)
90
ps
Data to Data Skew (t
DATA-MAX
− t
DATA-MIN
) Full
±50
±200
ps
Wake-Up Time (Standby)
25°C
250
ns
Wake-Up Time (Power-Down)
375
μs
Pipeline Latency
Full
16
Clock cycles
APERTURE
Aperture Delay (t
A
)
25°C
1
ns
Aperture Uncertainty (Jitter, t
J
) 25°C
135
fs
rms
Out-of-Range Recovery Time
25°C
1
Clock cycles
1
See the
, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4
t
SAMPLE
/16 is based on the number of bits in two LVDS data lanes. t
SAMPLE
= 1/f
S
.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS
Table 5.
Parameter
Description
Limit
Unit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK+ setup time
0.24
ns typ
t
HSYNC
SYNC to rising edge of CLK+ hold time
0.40
ns typ
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK
2
ns min
t
DH
Hold time between the data and the rising edge of SCLK
2
ns min
t
CLK
Period of the SCLK
40
ns min
t
S
Setup time between CSB and SCLK
2
ns min
t
H
Hold time between CSB and SCLK
2
ns min
t
HIGH
SCLK pulse width high
10
ns min
t
LOW
SCLK pulse width low
10
ns min
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 74)
SCLK falling edge (not shown in Figure 74)
10
ns min
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 74)
SCLK rising edge (not shown in Figure 74)
10
ns min