Atmel Evaluation Kit AT91SAM9G20-EK AT91SAM9G20-EK Fiche De Données

6413C–ATARM–18-Feb-09

Table 4-2.  JTAG/ICE Configuration

S1

Opened

Disables the ICE NTRST input

S2

Opened

Selects ICE Debug Mode or JTAG Boundary Scan Mode

S3

Opened

Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be unsoldered.

R13

Soldered

Enables the ICE RTCK return. S3 must be opened

R14

Soldered

Enables the ICE RTCK return. S3 must be opened

Table 4-3.  Microcontroller Clock Configuration

R18/R20

Soldered

Enables the use of 18.432MHz crystal. If external clock is used, R18/R20 
must be unsoldered and S4 closed.

S4

Opened

J9

Slow Clock Setting. See 

.

Table 4-4.  Memory Configuration

R31

R32

Soldered

Soldered

Enables MN7 Chip select access

Enables MN8 Chip select access

J34

R34

S6

Closed

Soldered

Opened

Enables the use of NAND Flash (MN6x)

Enables the use of Ready Busy signal

Disables write protect

J33

S5

Soldered

Opened

Enable the use of the Serial DataFlash®(MN9)

Disables write protect

R46

R47

Soldered

Soldered

Enables SCL access

Enables SDA access