Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Fiche De Données
Codes de produits
AT32UC3L0-XPLD
12
32099G–06/2011
AT32UC3L016/32/64
3.2.5
Oscillator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more
information about this.
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more
information about this.
3.2.6
Other Functions
The functions listed in
are not mapped to the normal GPIO functions.The aWire DATA
pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active
after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is
always enabled. Please refer to
after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is
always enabled. Please refer to
for constraints on the WAKE_N pin.
MDO[2]
PA16
PB03
MDO[1]
PA15
PB02
MDO[0]
PA14
PB09
EVTO_N
PA04
PA04
MCKO
PA06
PB01
MSEO[1]
PA07
PB11
MSEO[0]
PA11
PB12
Table 3-4.
Nexus OCD AUX Port Connections
Pin
AXS=1
AXS=0
Table 3-5.
Oscillator Pinout
48-pin
Pin
Oscillator Function
3
PA08
XIN0
46
PA10
XIN32
26
PA13
XIN32_2
2
PA09
XOUT0
47
PA12
XOUT32
25
PA20
XOUT32_2
Table 3-6.
Other Functions
48-pin
Pin
Function
27
PA11
WAKE_N
22
RESET_N
aWire DATA
11
PA00
aWire DATAOUT