Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Fiche De Données

32099G–06/2011

After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20,
even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by
the system to start other devices or to clock a switching regulator to rise the power supply volt-
age up to an acceptable value. 

The clock will be available on PA20, but will be disabled if one of the following conditions are
true:

• PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT)

• PA20 is configured as a General Purpose Input/Output (GPIO)

• The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power 

Manager chapter)

The maximum amplitude of the clock signal will be defined by VDDIN.

Once the RC32K output on PA20 is disabled it can never be enabled again. 

PA20 selects RC32OUT as default enabled after reset. This function is not automatically dis-
abled when the user enables the XOUT32_2 function on PA20. This disturbs the oscillator and
may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2
is enabled.

These pins are regular I/O pins powered from the VDDIO. However, when these pins are used
for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures
that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins
are not used for ADC inputs, the pins may be driven to the full I/O voltage range.