Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Fiche De Données

32099G–06/2011

The AVR32UC register file is shown below.

The AVR32UC Register File

The Status Register (SR) is split into two halfwords, one upper and one lower, see 

and 

. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,

and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.

The Status Register High Halfword

Interrupt Level 0 M ask
Interrupt Level 1 M ask

Interrupt Level 3 M ask

Interrupt Level 2 M ask

Initial value

Bit name

Mode Bit 0
Mode Bit 1

Mode Bit 2
Reserved

Debug State

Reserved

Exception Mask

Global Interrupt Mask

Debug State Mask

Secure State