Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Fiche De Données

32099G–06/2011

If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.

The FLO lock bit (FLOCR.LOCK) does not work
The FLO lock bit does not work and will always read as zero.
Fix/Workaround
Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.NOLOCK bit
to check if it is set. If it is set, a lock can not be obtained for this configuration of reference
clock and target ratio.

PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures. 
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.

The RC32K output on PA20 is not always permanently disabled
The RC32K output on PA20 may sometimes re-appear.
Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
to properly disable it:
- Run the CPU on RCSYS
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.

Reset may set status bits in the AST
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register before entering
sleep mode.

AST wake signal is released one AST clock cycle after the BUSY bit is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.