Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
Power Management
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
12-3
When the ARM926EJ-S has entered a low-power state, all of the main internal clocks
are stopped, including the clock for the ARM9EJ-S core. However, the ARM9EJ-S is
active if DBGTCKEN is asserted. This enables values to be written in the ARM9EJ-S
debug control register so that a debugger can force an exit from wait for interrupt mode.
This means that you can safely stop the ARM926EJ-S CLK if STANDBYWFI is
HIGH and DBGTCKEN is LOW.
are stopped, including the clock for the ARM9EJ-S core. However, the ARM9EJ-S is
active if DBGTCKEN is asserted. This enables values to be written in the ARM9EJ-S
debug control register so that a debugger can force an exit from wait for interrupt mode.
This means that you can safely stop the ARM926EJ-S CLK if STANDBYWFI is
HIGH and DBGTCKEN is LOW.
Figure 12-2 shows the recommended logic for stopping the main ARM926EJ-S clock
during wait for interrupt.
during wait for interrupt.
Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt
The nature of the nFIQ, nIRQ, and EDBGRQ signals enables them to be registered
prior to being used in the gating logic. DBGTCKEN must be used combinationally to
maintain the relationship between the ARM926EJ-S JTAG logic and the RTCK signal
used by the debugger. See the ARM9EJ-S Technical Reference Manual for details of
how DBGTCKEN is generated and used.
prior to being used in the gating logic. DBGTCKEN must be used combinationally to
maintain the relationship between the ARM926EJ-S JTAG logic and the RTCK signal
used by the debugger. See the ARM9EJ-S Technical Reference Manual for details of
how DBGTCKEN is generated and used.
12.1.2
Static power management (leakage control)
The ARM926EJ-S design is partitioned so that the SRAM blocks that are used for the
caches and the MMU can be powered down under certain conditions.
caches and the MMU can be powered down under certain conditions.
Cache RAMs
The RAMs for either of the caches can be safely powered down if the respective cache
has been disabled (using CP15 control register c1) and it contains no valid entries.
While a cache is disabled, only explicit CP15 operations can cause the cache RAMs to
be accessed (c7 cache maintenance operations). These instructions must not be
executed while any of the cache RAMs are powered down. If any of the RAMs for a
cache have been powered down, then they must be powered up prior to re-enabling the
relevant cache.
has been disabled (using CP15 control register c1) and it contains no valid entries.
While a cache is disabled, only explicit CP15 operations can cause the cache RAMs to
be accessed (c7 cache maintenance operations). These instructions must not be
executed while any of the cache RAMs are powered down. If any of the RAMs for a
cache have been powered down, then they must be powered up prior to re-enabling the
relevant cache.
DBGTCKEN
STANDBYWFI
FCLK = Free running clock
CLK
FCLK
nFIQ
nIRQ
EDBGRQ
CLK = Clock supplied to ARM926EJ-S macrocell
FCLK
HRESETn
EN
RST