Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
Signal Descriptions
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
A-5
A.3
Coprocessor interface signals
Table A-2 describes the ARM926EJ-S processor coprocessor interface signals.
Table A-2 Coprocessor interface signals
Name
Direction
Description
CPABORT
Output
Indicates
STC
/
LDC
operation aborted. Asserted in WB
stage of coprocessor pipeline.
CPBURST[3:0]
Output
Indicates number of words to be transferred for
LDC
/
STC
operation. If no external coprocessors are
attached, this must be tied to b0000.
CPCLKEN
Coprocessor clock
enable
enable
Output
Coprocessor clock enable. When HIGH on the rising
edge of CLK the pipeline follower logic can
advance.
edge of CLK the pipeline follower logic can
advance.
CPDIN[31:0]
Coprocessor write data
Input
The coprocessor data bus for transferring data from
the coprocessor.
the coprocessor.
CPDOUT[31:0]
Coprocessor read data
Output
The coprocessor data bus for transferring data to the
coprocessor.
coprocessor.
CPEN Coprocessor
enable
enable
Input
When LOW disables the external coprocessor
interface. If CPEN is LOW then CHSDE and
CHSEX must both be driven to b10 (ABSENT
response).
interface. If CPEN is LOW then CHSDE and
CHSEX must both be driven to b10 (ABSENT
response).
CPINSTR[31:0]
Coprocessor
instruction data
instruction data
Output
The coprocessor instruction bus that instructions are
transferred over to the pipeline follower in the
coprocessor.
transferred over to the pipeline follower in the
coprocessor.
CPPASS
Output
Indicates that there is a coprocessor instruction in the
Execute stage of the pipeline, that must be executed.
Execute stage of the pipeline, that must be executed.
CPLATECANCEL
Output
If HIGH during the first Memory cycle of a
coprocessor instruction, then the coprocessor must
cancel the instruction without changing any internal
state.
coprocessor instruction, then the coprocessor must
cancel the instruction without changing any internal
state.
CHSDE[1:0]
Coprocessor
handshake decode
handshake decode
Output
The handshake signals from the Decode stage of the
coprocessor pipeline follower. Indicates ABSENT
(b10), WAIT (b00), GO (b01), or LAST (b11). If no
external coprocessors are attached this must be tied to
b10 (ABSENT response).
coprocessor pipeline follower. Indicates ABSENT
(b10), WAIT (b00), GO (b01), or LAST (b11). If no
external coprocessors are attached this must be tied to
b10 (ABSENT response).