Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-27
The first four bits of this register determine the L bit for the associated cache way. The
Opcode_2 field of the MRC or MCR instruction determines whether the instruction or
data lockdown register is accessed:
Opcode_2 field of the MRC or MCR instruction determines whether the instruction or
data lockdown register is accessed:
Opcode_2 = 0
Selects the DCache lockdown register.
Opcode_2 = 1
Selects the ICache lockdown register.
You can use the instructions shown in Table 2-20 to access the Cache Lockdown
Register.
Register.
You must only modify the Cache Lockdown Register using a read-modify-write
sequence. For example:
sequence. For example:
MRC p15, 0, <Rn>, c9, c0, 1 ;
ORR <Rn>, <Rn>, 0x01 ;
MCR p15, 0, <Rn>, c9, c0, 1 ;
ORR <Rn>, <Rn>, 0x01 ;
MCR p15, 0, <Rn>, c9, c0, 1 ;
This sequence sets the L bit to 1 for way 0 of the ICache. The format of the cache
lockdown register c9 is shown in Figure 2-12.
lockdown register c9 is shown in Figure 2-12.
Figure 2-12 Cache Lockdown Register c9 format
Table 2-20 Cache Lockdown Register instructions
Function
Data
Instruction
Read DCache Lockdown Register
L bits
MRC p15,0,<Rd>,c9,c0,0
Write DCache Lockdown Register
L bits
MCR p15,0,<Rd>,c9,c0,0
Read ICache Lockdown Register
L bits
MRC p15,0,<Rd>,c9,c0,1
Write ICache Lockdown Register
L bits
MCR p15,0,<Rd>,c9,c0,1
SBZ/UNP
31
16 15
4 3
0
SBO
L bits
(cache ways
0 to 3)