Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO Fiche De Données
Codes de produits
ATSAM4S-XPRO
773
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Figure 36-20. Synchronous Mode Character Reception
36.7.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the
RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is
set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by
writing US_CR with the RSTSTA (Reset Status) bit to 1.
Figure 36-21. Receiver Status
36.7.3.8 Parity
The USART supports five parity modes that are selected by writing to the PAR field in the US_MR. The PAR field
also enables the multidrop mode, see “Multidrop Mode” on page 774. Even and odd parity bit generation and error
detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit
is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity
generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error
if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit
to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is
disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Sampling
Parity Bit
Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0
D1
D2
D3
D4
D5
D6
D7
Start
Bit
Parity
Bit
Stop
Bit
RSTSTA = 1
Read
US_RHR