Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO Fiche De Données
Codes de produits
ATSAM4S-XPRO
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
832
37.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Timer Counter clock.
37.5.3 Interrupt
The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires
programming the IC before configuring the TC.
37.5.4 Fault Output
The TC has the FAULT output internally connected to the fault input of PWM. Refer to
and to the product Pulse Width Modulation (PWM) implementation.
37.6
Functional Description
37.6.1 TC Description
The 3 channels of the Timer Counter are independent and identical in operation except when quadrature decoder
is enabled. The registers for channel programming are listed in
.
37.6.2 16-bit Counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge
of the selected clock. When the counter has reached the value 2
16
-1 and passes to zero, an overflow occurs and
the COVFS bit in the TC Status Register (TC_SR) is set.
The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The
The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The
counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the
selected clock.
37.6.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC
Block Mode Register (TC_BMR). See
.
Each channel can independently select an internal or external clock source for its counter:
•
Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4,
TIMER_CLOCK5
TIMER_CLOCK5
•
External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR).
The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges
The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges
of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the
TC_CMR defines this signal (none, XC0, XC1, XC2). See
Note:
In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period.
The external clock frequency must be at least 2.5 times lower than the master clock
TC1
TIOB3
PC24
B
TC1
TIOB4
PC27
B
TC1
TIOB5
PC30
B
Table 37-4.
I/O Lines (Continued)