Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
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Codes de produits
AT91SAM9N12-EK
165
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
20.4
Slow Clock Controller (SCKC) User Interface
Table 20-1. Register Mapping
Offset
Register
Name
Access
Reset
0x0
Slow Clock Configuration Register
SCKC_CR
Read-write
0x0000_0001