Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
198
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
• MDIV: Master Clock Division
• PLLADIV2: PLLA divisor by 2
Value
Name
Description
0
EQ_PCK
Master Clock is Prescaler Output Clock divided by 1.
Warning: DDRCK is not available.
1
PCK_DIV2
Master Clock is Prescaler Output Clock divided by 2.
DDRCK is equal to MCK.
2
PCK_DIV4
Master Clock is Prescaler Output Clock divided by 4.
DDRCK is equal to MCK.
3
PCK_DIV3
Master Clock is Prescaler Output Clock divided by 3.
DDRCK is equal to MCK.
Value
Name
Description
0
NOT_DIV2
PLLA clock frequency is divided by 1.
1
DIV2
PLLA clock frequency is divided by 2.