Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données

Codes de produits
AT91SAM9N12-EK
Page de 1104
437
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the
SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the
SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the
lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to
provide the maximum throughput for the SDRAM device, arbitration may only take place during the following cycles:
1.
Idle cycles: When no master is connected to the SDRAM device.
2.
Single cycles: When a slave is currently doing a single access.
3.
End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, pre-
dicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is 
generated at the end of each four beat boundary inside the INCR transfer.
4.
Anticipated Access: When an anticipate read access is done while current access is not complete, the arbitration 
scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme.
Figure 31-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
NOP
READ
NOP
0
NOP
PRECH
ACT
READ
1
1
2
Anticipate command, Precharge/Active Bank 2
Trp
Read access in Bank 1
SDClK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Di
Dj
Dk
Dl
D[15:0]
3
DM1:0]