Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données
Codes de produits
AT91SAM9N12-EK
468
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 32-5. Multi Buffer Transfer Using Linked List
Descriptor Integrity Check
When the Descriptor Integrity Check is enabled, a cyclic redundancy check information is attached to the descriptor.
When fetched from the memory, the descriptor is verified through the use of a CRC16-CCIT (0x1021 polynom) by the
DMAC channel. If a CRC error is detected, then the DICERR flag is set in the DMAC_EBCISR register. The CRC16 is
computed from MSB to LSB. The BTSIZE and DONE fields of the DMAC_CTRLAx register are ignored and set to zero.
When fetched from the memory, the descriptor is verified through the use of a CRC16-CCIT (0x1021 polynom) by the
DMAC channel. If a CRC error is detected, then the DICERR flag is set in the DMAC_EBCISR register. The CRC16 is
computed from MSB to LSB. The BTSIZE and DONE fields of the DMAC_CTRLAx register are ignored and set to zero.
Figure 32-6. Linked List with CRC16 Attached
System Memory
SADDRx
= DSCRx(0) + 0x0
DADDRx
= DSCRx(0) + 0x4
CTRLAx
= DSCRx(0) + 0x8
CTRLBx
= DSCRx(0) + 0xC
DSCRx(1)
= DSCRx(0) + 0x10
SADDRx
= DSCRx(1) + 0x0
DADDRx
= DSCRx(1) + 0x4
CTRLBx
= DSCRx(1) + 0x8
CTRLBx
= DSCRx(1) + 0xC
DSCRx(2)
= DSCRx(1) + 0x10
DSCRx(0)
DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor
(points to 0 if
LLI(1) is the last
transfer descriptor
DSCRx(1)
LLI(0)
LLI(1)
System Memory
SADDRx
= DSCRx(0) + 0x0
DADDRx
= DSCRx(0) + 0x4
CTRLAx
= DSCRx(0) + 0x8
CTRLBx
= DSCRx(0) + 0xC
DSCRx(1)
= DSCRx(0) + 0x10
SADDRx
= DSCRx(1) + 0x0
DADDRx
= DSCRx(1) + 0x4
CTRLBx
= DSCRx(1) + 0x8
CTRLBx
= DSCRx(1) + 0xC
DSCRx(2)
= DSCRx(1) + 0x10
DSCRx(0)
DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor
(points to 0 if
LLI(1) is the last
transfer descriptor
DSCRx(1)
LLI(0)
LLI(1)
CRCx(1)
= DSCRx(0) + 0x14
CRCx(2)
= DSCRx(1) + 0x14