Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Fiche De Données
Codes de produits
AT91SAM9M10-G45-EK
379
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
27.8.2
SPI Mode Register
Name:
SPI_MR
Addresses:
0xFFFA4004 (0), 0xFFFA8004 (1)
Access:
Read/Write
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data.
This mode prevents overrun error in reception.
This mode prevents overrun error in reception.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled
31
30
29
28
27
26
25
24
DLYBCS
23
22
21
20
19
18
17
16
–
–
–
–
PCS
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
LLB
–
WDRBT
MODFDIS
–
PCSDEC
PS
MSTR