Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Fiche De Données
Codes de produits
ATSAM4S-XPLD
465
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to Main Clock or Slow Clock,
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in the PMC_SR.
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage one of the following parameters, CSS or PRES is modified, the MCKRDY bit
will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The
user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The
user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
Note:
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing
in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked
again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock.
For further information, see
in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked
again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock.
For further information, see
.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 2.
The Processor Clock is the Master Clock.
5.
Selection of Programmable Clocks
Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. 3
Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication
as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication
as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
Programmable Clock Registers (PMC_PCKx) are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are
available: main clock, slow clock, PLLACK, PLLBCK. By default, the clock source selected is
slow clock.
available: main clock, slow clock, PLLACK, PLLBCK. By default, the clock source selected is
slow clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input
divided by PRES parameter. By default, the PRES parameter is set to 0 which means that
master clock is equal to slow clock.
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input
divided by PRES parameter. By default, the PRES parameter is set to 0 which means that
master clock is equal to slow clock.
Once PMC_PCKx has been programmed, The corresponding Programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in PMC_SR. This
can be done either by polling the status register or by waiting the interrupt line to be raised, if
the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parame-
ters in PMC_PCKx can be programmed in a single write operation.
enabled and the user is constrained to wait for the PCKRDYx bit to be set in PMC_SR. This
can be done either by polling the status register or by waiting the interrupt line to be raised, if
the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parame-
ters in PMC_PCKx can be programmed in a single write operation.
If the CSS and PRES parameters are to be modified, the corresponding Programmable clock
must be disabled first. The parameters can then be modified. Once this has been done, the
user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.
must be disabled first. The parameters can then be modified. Once this has been done, the
user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.
6.
Enabling Peripheral Clocks