Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Fiche De Données

Codes de produits
ATSAM4S-XPLD
Page de 1125
 709
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:
Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) 
with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will 
not provide a time-out. This prevents having to handle an interrupt before a character is received and allows 
waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload 
and Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value 
TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no 
key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the
start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of
the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a
periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. 
Figure 35-24.Receiver Time-out Block Diagram 
Table 35-11. Maximum Time-out Period  
Baud Rate
Bit Time
Time-out
bit/sec
μs
ms
600
1 667
109 225
1 200
833
54 613
2 400
417
27 306
4 800
208
13 653
9 600
104
6 827
14400
69
4 551
19200
52
3 413
28800
35
2 276
33400
30
1 962
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
D
Q
1
Clear