Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Fiche De Données
Codes de produits
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
462
26.12.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal,
the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When
the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the
point where it was stopped. See
. This mode must be selected when the external device uses the
NWAIT signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in
.
Figure 26-23. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
NCS_WR_PULSE = 7
A[23:0]
MCK
NWE
NCS
4
3
2
1
1
1
0
1
4
5
6
3
2
2
2
2
1
0
Write cycle
D[7:0]
NWAIT
FROZEN STATE
internally synchronized
NWAIT signal