Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Fiche De Données

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

To configure the automatic update, the user must define a value for the Update Period by the field UPR in the 

PWM_SCUP register. The PWM controller waits UPR+1 periods of synchronous channels before updating 

automatically the duty values and the update period value.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly 

reduces the number of clock cycles required for a data transfer, which improves microcontroller performance.
The PDC must write the duty-cycle values in the synchronous channels index order. For example if the channels 0, 

1 and 3 are synchronous channels, the PDC must write the duty-cycle of the channel 0 first, then the duty-cycle of 

the channel 1, and finally the duty-cycle of the channel 3.
The status of the PDC transfer is reported in the PWM_ISR2 by the following flags:



WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new 

update period value. It is reset to ‘0’ when the PWM_ISR2 is read. The user can choose to synchronize the 

WRDY flag and the PDC transfer request with a comparison match (see 

), by the fields PTRM and PTRCS in the PWM_SCM register.



ENDTX : this flag is set to ‘1’ when a PDC transfer is completed



TXBUFE : this flag is set to ‘1’ when the PDC buffer is empty (no pending PDC transfers)



UNRE: this flag is set to ‘1’ when the update period defined by the UPR field has elapsed while the whole 

data has not been written by the PDC. It is reset to ‘0’ when the PWM_ISR2 is read.

Depending on the interrupt mask in the PWM_IMR2, an interrupt can be generated by these flags. 
Sequence for Method 3:

1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the 

PWM_SCM register.

2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in the update period 

by the PTRM bit and the PTRCS field in the PWM_SCM register (at the end of the update period or when a 

comparison matches).

5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC registers
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write registers that need to be 

updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to 

8. Set UPDULOCK to ‘1’ in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit 

UPDULOCK is reset, go to 

 for new values.

10. If an update of the update period value is required, check first that write of a new update value is possible by 

polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2, else go to 

11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous channels when the Update 

Period is elapsed. Go to 

 for new values.

13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define a new PDC transfer 

in the PDC registers for new duty-cycle values. Go to