Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données
Codes de produits
AT32UC3A3-XPLD
102
32072H–AVR32–10/2012
AT32UC3A3
10.6.2
Interrupt Request Registers
Name:
IRR0...IRR63
Access Type: Read-only
Offset:
0x0FF - 0x1FC
Reset Value:
N/A
• IRR: Interrupt Request line
This bit is cleared when no interrupt request is pending on this input request line.
This bit is set when an interrupt request is pending on this input request line.
The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible
input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The
IRRs are sampled continuously, and are read-only.
31
30
29
28
27
26
25
24
IRR[32*x+31]
IRR[32*x+30]
IRR[32*x+29]
IRR[32*x+28]
IRR[32*x+27]
IRR[32*x+26]
IRR[32*x+25]
IRR[32*x+24]
23
22
21
20
19
18
17
16
IRR[32*x+23]
IRR[32*x+22]
IRR[32*x+21]
IRR[32*x+20]
IRR[32*x+19]
IRR[32*x+18]
IRR[32*x+17]
IRR[32*x+16]
15
14
13
12
11
10
9
8
IRR[32*x+15]
IRR[32*x+14]
IRR[32*x+13]
IRR[32*x+12]
IRR[32*x+11]
IRR[32*x+10]
IRR[32*x+9]
IRR[32*x+8]
7
6
5
4
3
2
1
0
IRR[32*x+7]
IRR[32*x+6]
IRR[32*x+5]
IRR[32*x+4]
IRR[32*x+3]
IRR[32*x+2]
IRR[32*x+1]
IRR[32*x+0]