Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données
Codes de produits
AT32UC3A3-XPLD
170
32072H–AVR32–10/2012
AT32UC3A3
ured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data
Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address
space must be written as shown in
Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address
space must be written as shown in
to enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set
in Byte Select mode on the corresponding Chip Select.
in Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the SMC Section.
details on these waveforms and timings, refer to the SMC Section.
14.6.5.3
Read/Write signals
During read operations, in I/O mode, the CompactFlash logic drives the read command signals
of the SMC on CFNIORD signal, while the CFNOE is deactivated. Likewise, in common memory
mode and attribute memory mode, the SMC signals are driven on the CFNOE signal, while the
CFNIORD is deactivated.
of the SMC on CFNIORD signal, while the CFNOE is deactivated. Likewise, in common memory
mode and attribute memory mode, the SMC signals are driven on the CFNOE signal, while the
CFNIORD is deactivated.
demonstrates a schematic representation of
this logic.
During write operations, in all modes, the CompactFlash logic drives the write command signal
of the SMC on CFNWE signal. Addtionnal external logic is required to drive _WE and _IOWR
compact flash signals based on CFNWE.
of the SMC on CFNWE signal. Addtionnal external logic is required to drive _WE and _IOWR
compact flash signals based on CFNWE.
representation of this logic. No external logic is required if I/O mode is not used (in this case,
CNFWE signal can drive directly _WE compact flash signal).
CNFWE signal can drive directly _WE compact flash signal).
Attribute memory mode, common memory mode and I/O mode are supported by writing the
address setup and hold time on the NCS[4] (and/or NCS[5]) chip select to the appropriate val-
ues. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles
of the SMC Section.
address setup and hold time on the NCS[4] (and/or NCS[5]) chip select to the appropriate val-
ues. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles
of the SMC Section.
Table 14-5.
CFCE1 and CFCE2 Truth Table
Mode
CFCE2
CFCE1
DBW
Comment
SMC Access
Mode
Mode
Attribute Memory
NBS1
NBS0
16 bits
Access to Even Byte on
DATA[7:0]
DATA[7:0]
Byte Select
Common Memory
NBS1
NBS0
16bits
Access to Even Byte on
DATA[7:0]
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
DATA[15:8]
Byte Select
1
0
8 bits
Access to Odd Byte on
DATA[7:0]
DATA[7:0]
I/O Mode
NBS1
NBS0
16 bits
Access to Even Byte on
DATA[7:0]
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
DATA[15:8]
Byte Select
1
0
8 bits
Access to Odd Byte on
DATA[7:0]
DATA[7:0]