Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données

32072H–AVR32–10/2012

 shows an example of SDRAM device connection using a 16-bit data

bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.

Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width

The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR). 

The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.

 to 

 illustrate the SDRAM device memory map-

ping seen by the user in correlation with the device structure. Various configurations are
illustrated.

DQM[1:0]

Data Mask Enable Signals

Output

High

SDRAMC_A[12:0]

Address Bus

Output

D[15:0]

Data Bus

Input/Output

I/O Lines Description

2Mx8

SDRAM

D0-D7

CS

DQM

CLK

CKE
WE

RAS
CAS

A0-A9 A11

BA0

A10

BA1

SDRAMC_A10

BA0

BA1

2Mx8

SDRAM

D0-D7

CS

DQM

CLK

CKE
WE

RAS
CAS

A0-A9 A11

BA0

A10

BA1

SDRAMC_A10

BA0

BA1

SDCS

BA1

BA0

SDRAMC_A[0-12]

SDRAM

Controller

DQM[0-1]

SDWE

SDCKE

SDCK

CAS

RAS

D0-D31

DQM0

D0-D7

D8-D15

DQM1